International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - Hardware Efficient Low Power Multi-Favour Network-on-chip Smart Router on FPGA Chip
Router plays a major role to select and forward data from source to destination or intermediate node in
communication system. Not only delay, but also area and power of router are important for hardware design. It is possible to
integrate hundreds of billions of transistors in single chip or system on chip (SoC) with interconnects, infrastructure and
memory. Interconnect consumes a large amount of area and power. Network-on-chip (NoC) is an on-chip communication
device, which is alternate for SoCs. In this paper, we present a multi-favour NoC router that improves area and power
without compromising latency. The first contribution of this work is to propose a new parallel buffer structure with buffer
management algorithm to improve the efficiency of NoC communication. The second contribution is that combined virtual
channel and switch (VC/SW) allocation, which reduce the hardware utilization. The proposed NoC router is executed on
different FPGA expertise in Xilinx tool. The simulation results show that the performance of proposed NoC router performs
very effective in terms of hardware utilization, power and delay compare to existing router design.
Keywords - Multi-favour NoC Router, combined virtual channel and switch allocation, reallocated buffer design, buffer
management algorithm, and vertex4 FPGA family.
Author - Ananth Kumar M S, Jayadevappa D
Citation - Ananth Kumar M S ,
Jayadevappa D ,
Ananth Kumar M S, Jayadevappa D " Hardware Efficient Low Power Multi-Favour Network-on-chip Smart Router on FPGA Chip " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-5,Issue-6 ( Jun, 2017 )