International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - Full Adder/Subtractor Circuit Using Reversible Logic Gates
Reversible logic has become one of the most promising areas in the past few decades and has found its
application in several technologies. Reversible circuits outperform irreversible circuits in terms of power and delay. This
paper presents a novel way of designing 1-bit and 4-bit adder / subtractor using the HNG gate and Perez Gate employing a 6
Transistor approach rather than using the conventional 8 transistor reversible logic. Thereby reducing the number of
transistors. Power dissipation and delay are calculated for 1-bit and 4-bit adders using both HNG and Perez gate for various
technologies such as 0.35um, 0.18um and 0.6um for 5v, 4v, 3.3v and 3v. The results are obtained using Mentor Graphics
tool and has shown significant improvement in terms of power dissipation and delay compared to the irreversible circuits.
Keywords— Full Adders, Full Subtractors, Reversible Logic, 4-Bit Adder, 1-Bit Adder, 4-Bit Subtractor,1-Bit Subtractor,
HNG Gate, Perez Gate, Feymann Gate, Ripple Carry Adder.
Author - Pradeesha R. Chandran, Anand Kumar, Arti Noor
Citation - Pradeesha R. Chandran ,
Anand Kumar ,
Arti Noor ,
Pradeesha R. Chandran, Anand Kumar, Arti Noor " Full Adder/Subtractor Circuit Using Reversible Logic Gates " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-4,Issue-7 ( Jul, 2016 )