Journal Paper

Paper Title - Design Of Speed And Power Efficient 64x64 Bit Urdhva Tiryakbyham Multiplier


Abstract
Multipliers are one of the most widely used digital component in the digital integrated circuit design and are the necessary part of many digital signal processing applications such as correlations, convolution, filtering, frequency analysis, image processing etc. with advances in technology, researchers have tried and are trying to design multipliers which offer either high speed, low power consumption, less area or combination of them. This paper focus on the development of high speed low power multiplier using Vedic mathematics. The proposed 64X64 bit multiplier architecture is designed using modified full adder carry save adder and it achieves 60% improvement in speed and 37% improvement in power as compared with that of conventional array multipliers. Keyword- Vedic Mathematics, Urdhva tiryakbyham, Carry save adder.


Author - Navyashree Hosamane, G.Jyothi, M Z Kurianf

Citation - Navyashree Hosamane   ,   G.Jyothi   ,   M Z Kurianf   ,   Navyashree Hosamane, G.Jyothi, M Z Kurianf " Design Of Speed And Power Efficient 64x64 Bit Urdhva Tiryakbyham Multiplier " , International Journal of Industrial Electronics and Electrical Engineering , Volume-3, Issue-5  ( May, 2015 )

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| Published on 2015-05-11