International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
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Paper Title - Fault Injection Technique in Functional RTL Code for Sequential ATPG
Abstract - Fault injection is mainly used to evaluate the fault tolerance and to determine the fault propagation, and fault coverage. Automatic Test Pattern Generation (ATPG) is becoming increasingly important because the scan-based structure has problems with performance, overhead, over-testing, power consumption during testing. Here, stuck-at faults are used to insert a fault in the ISCAS’89 benchmark circuits and the faults are injected using the AND, OR logic gates. Then, those circuits are simulated and output is verified to check the fault injection. A scan-chain-based netlist is generated to improve the controllability and observability. A test vector is generated using the Cadence MODUS tool and then the fault coverage and Test time are evaluated from the results of some ISCAS’89 benchmark circuits and also from the Proposed design. The proposed design is a combination of s27, s298, s444 ISCAS’89 Benchmark Circuits. This shows that permanent faults are injected in the block and the coverage states that the time required to find the test patterns is difficult when multiple number of faults are injected in the design which is demonstrated by the test time.
Keywords - Stuck-at fault, Permanent fault, Controllability, Observability, Automatic Test Pattern Generation (ATPG), Test time, Fault Coverage.
Author - Nemalapuri Chaitanya, Shashidhar Tantry
Citation - Nemalapuri Chaitanya ,
Shashidhar Tantry ,
Nemalapuri Chaitanya, Shashidhar Tantry " Fault Injection Technique in Functional RTL Code for Sequential ATPG " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-9,Issue-12 ( Dec, 2021 )