International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - Power Analysis Of CMOS And Adiabatic Logic Design
The main objecive of this paper is to provide new low power solutions for Very Large Scale Integration (VLSI)
designers. Especially, this work focuses on the reduction of the power dissipation, which is showing an ever-increasing
growth with the scaling down of the technologies. Then, to limit the power dissipation, alternative solutions at each level of
abstraction are proposed. The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the
design of personal information systems and large computers. In this paper, a new CMOS logic family called ADIABATIC
LOGIC, based on the adiabatic switching principle is presented. The Logic cells like 2N2P, 2N2N2P, PFAL has been
designed and presented here. Power consumption is widely reduced upto50%. The simulation tool used to design Adiabatic
cell is TANNER EDA V13.0 Technology.
Author - Premchand D.R, Siddalingamma
Citation - Premchand D.R ,
Premchand D.R, Siddalingamma " Power Analysis Of CMOS And Adiabatic Logic Design " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-2,Issue-9 ( Sep, 2014 )