Paper Title
Implementation Of High Speed Enhanced Csla Based On Gated D-Latch

Adder plays an important role in any part of the computational systems like addition, subtractions, high speed multiplications, DSPs and ALUs. There are several types of adders like Parallel Adder, Ripple-Carry Adder (RCA), Carry Look-Ahead Adder (CLA), Carry Save Adder (CSA), Carry Select Adder (CSLA) etc. Each adder has their own performance in reducing parameters like area, delay and power. From the structure of CSLA, there is a scope of modifying circuit in turn which increases the speed. Speed is one among the various VLSI parameters which is dealt in this project “Implementation of High Speed Enhanced CSLA Based on Gated D-Latch”. Carry Select Adder is the fast adder used for fast arithmetic functions in the data processors compared to other conventional adders. Gated D-Latch was replaced instead of RCA with carry-in as ‘1’ in Regular CSLA (RCSLA) and BEC in Modified CSLA (MCSLA). In this project 16-bit, 32- bit and 64-bit Enhanced CSLA (ECSLA) have been developed and had better out comes compared with RCSLA and MCSLA. Thus if we compare with MCSLA the proposed system ECSLA is about 52.753% faster and 34.993% faster than RCSLA. The project was simulated and synthesized using Xilinx ISE Design Suite 14.4 and implemented on Xilinx-Spartan 3E-FPGA kit. Keywords- Enhanced CSLA (ECSLA), Gated D-Latch, Modified CSLA (MCSLA), Regular CSLA (RCSLA), Xilinx ISE Design Suite 14.4.