International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - VLSI Implementation Of Low-Cost Fir Filter Structure Based On Improved Faithfully Rounded Truncated Multiplier
This paper presents the design of low-cost FIR filter structure based on Improved Faithfully rounded truncated
multiplier. The Improved truncated multiplier design reduces the area and power consumption by computing the most
significant part of Partial Product Bit (PPB) matrix and also minimizes the number of full adders and half adders used for
compression of PPB matrix. In the proposed multiplier design, the least significant part of PPB matrix is significantly
compressed by jointly considering deletion, truncation, and rounding. The total truncation error of improved truncated
multiplier is not more than 1ulp (unit of least position) so this design gives the precised output. The FIR filter design is
realized using improved truncated multiplier which achieves better area and power results. This design is simulated and
synthesized using XILINX ISE software.
Author - P.Kavitha, R.Ramesh
Citation - P.Kavitha ,
P.Kavitha, R.Ramesh " VLSI Implementation Of Low-Cost Fir Filter Structure Based On Improved Faithfully Rounded Truncated Multiplier " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-2,Issue-5 ( May, 2014 )