International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - Power Optimization in System on Chip by Implementation of Efficient Cache Architecture
In advanced multimedia communication based systems, performance improvement is one of the most important
issues. Data cache consumes a major portion of the whole processor power for communication applications as they are
mainly data intensive. The cache architecture cannot be taken care of specifically for an application in case of an integrated
communication system. As a result, a big amount of cache memory is not used. In this paper, the software-controlled cache
architecture has been proposed, that improves the energy efficiency of the shared cache in an integrated communication
based system. For different cache regions, data types are allocated for an application. Only the allocated cache regions are
activated. The effectiveness of software-controlled cache after integration is tested in a communication based system on
chip. The results show the performance improvement of the system on chip up-to a huge level on ARM-
like cache architecture.
Index Terms— Performance Improvement, Cache Memory, Energy Efficiency, Software Cache.
Author - Akkala Subba Rao, Pratik Ganguly
Citation - Akkala Subba Rao ,
Pratik Ganguly ,
Akkala Subba Rao, Pratik Ganguly " Power Optimization in System on Chip by Implementation of Efficient Cache Architecture " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-5,Issue-1 ( Jan, 2017 )