Journal Paper

Paper Title - Performance Analysis of Different Adders Using FPGA


Abstract
Adders being the building blocks of any microprocessor and digital component, so fast and accurate operation of digital system are greatly influenced by the performance of the resident adders. Therefore designers are trying to design different adders which lead to low power, high speed and less area. This project describes the analysis of speed, area and delay of different types of adder like carry-look ahead adder, carry skip adder, ripple carry adder and carry select adder for 8, 16, 32 and 64 bit. Depending on experimental analysis, for 64 bit RCA have simplest architecture but highest carry propagation delay of 100%. CSKA performs fast addition; it greatly reduces the delay with special speed up carry chain called a skip chain, as the carry bit for each block can be bypassed (skip) over the blocks and has propagation delay of 63.75%. CSLA performs fast addition where adders are split in blocks of N by half or variable length and there partial sum, true sum and carry are calculated by parallel addition with carry in for 0 and for 1.Final result is selected by the multiplexer and its having delay of 9.01% for 64 bit. Various adders are designed using Verilog HDL. Then, they are simulated and synthesized using Xilinx ISE 12.2 for Vertex 6 family with device speed grade -3. Index Terms— RCA-Ripple carry adder; CLA-Carry look ahead adder; CSKA-Carry skip adder; CSLA-Carry select adder.


Author - J. M .Rudagi, Kavitha, Keerti Savakar, Chiranjeevi Malli, Bharath Hawaldar

Citation - J. M .Rudagi   ,   Kavitha   ,   Keerti Savakar   ,   Chiranjeevi Malli   ,   Bharath Hawaldar   ,   J. M .Rudagi, Kavitha, Keerti Savakar, Chiranjeevi Malli, Bharath Hawaldar " Performance Analysis of Different Adders Using FPGA " , International Journal of Industrial Electronics and Electrical Engineering , Volume-4,Issue-8  ( Aug, 2016 )

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| Published on 2016-09-26