International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - SRAM Memory Testing Technique Using BISR Scheme
Random Access Memory is major component in present day SOC, by Improving the yield of RAM improves the
yield of SOC. So the repairable memories play a vital role in improving the yield of chip. Built-in self-repair (BISR) technique
has been widely used to repair embedded random access memories (Ram's). If each repairable RAM uses one self contained
BISR circuit (Dedicated BISR scheme), then the area cost of BISR circuits in an SOC becomes high. This, results in converse
effect in the yield of Ram's. This paper presents a reconfigurable BISR (Re-BISR) scheme for repairing RAMs with different
sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of
defective Ram's. In the Re-BISR, a reconfigurable built-in redundancy analysis (Re-BIRA) circuit is designed to perform the
redundancy algorithm for various Ram's. A built-in self-repair (BISR) scheme for random access memories (Ram's) with 2-D
redundancy has a built-in redundancy analyser (BIRA) for allocating the redundancy. The BIRA typically has a cache-like
element called local bitmap for storing the fault information temporary. The BISR reuses the local bitmap to serve as spare
bits such that it can repair more faults. In addition, a row/column/bit redundancy analysis (RCB-RA) algorithm for a RAM
with spare rows, spare columns, and spare bits is presented. The Re-BISR structure has been synthesized and found that the
area cost when compared with the Dedicated BISR structure is very small. This paper is implemented using Verilog HDL.
Simulation and Synthesis is done using Model Sim and Xilinx ISE.
Index Terms — About Four Key Words or Phrases in Alphabetical Order, Separated by Commas.
Author - B.Malleswari, G.Shanthi
Citation - B.Malleswari ,
B.Malleswari, G.Shanthi " SRAM Memory Testing Technique Using BISR Scheme " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-3,Issue-12 ( Dec, 2015 )