International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - A Low Noise-Low Power-Variable Gain Amplifier Using 0.13μm CMOS Technology
A Low noise, Low power, variable gain amplifier is designed using TSMC 0.13μM CMOS technology. In this
design four stages of attenuators are used and the output of two stage amplifier is applied to it. Attenuators are used for
obtaining variation in gain while amplifiers are used for high gain, high linearity and low noise figure. The design operates on
frequency range of 40MHz to 950MHz. The power consumption achieved is less than 10mW and dynamic gain range is about
55dB. The variable gain obtained is -24 to 30 dB at 40MHz and -27 to 26 dB at 950 MHz. The noise figures of this design is 2
dB and the third order Intercept point (IIP3) is 6.2 dBm at maximum gain of 30dB.
Index Terms- Variable Gain Amplifier, Attenuator, Power Consumption, Noise Figure.
Author - Pratik R. Junwar, Usha Verma
Citation - Pratik R. Junwar ,
Usha Verma ,
Pratik R. Junwar, Usha Verma " A Low Noise-Low Power-Variable Gain Amplifier Using 0.13μm CMOS Technology " ,
International Journal of Industrial Electronics and Electrical Engineering , Volume-3,Issue-11 ( Nov, 2015 )