International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - Design And Implementation Of Online BIST Using ALU
Transparent BIST schemes for RAM modules assure the preservation of the memory contents during
periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in
traditional transparent BIST, achieving considerable reduction in test time. Previous works on both offline MARCH-C
testing scheme and online testing symmetric transparent BIST schemes require that a separate BIST module is utilized for
each RAM under test. This approach, given the large number of memories available in current chips, increases the
hardware overhead of the BIST circuitry. In this paper we propose a Symmetric transparent online BIST scheme that is
used to test RAMs of different word widths; hence, more than one RAMs can be tested in a roving manner and here in this
paper we are testing 5 RAMs of word lengths 3 bit to 7 bit . The hardware used for proposed scheme is smaller compared to
the previously utilized proposed symmetric transparent schemes, for typical memory configurations.
Author - M.S.Pavan Kumar, A.Sivaiah
Citation - M.S.Pavan Kumar ,
M.S.Pavan Kumar, A.Sivaiah " Design And Implementation Of Online BIST Using ALU " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-2,Issue-9 ( Sep, 2014 )