Paper Title - Conditional Data D Flip-Flop Design Using Pass Transistors For Low Power Application


Abstract
Power reduction in an IC is a serious concern now days. As the MOS devices are wide spread, there is high need for circuits which consume less power, mainly for portable devices which run on batteries, like Laptops and hand-held computers. The memory elements consume 70 percent of the total power in an IC. As flip-flops are the major sector of the memory elements used in any portable devices, the major concern to reduce the power consumption in flip-flops will help us to reduce the power consumption in an IC to a major extent. And reducing the number of clocked transistors give us good results in reduction of its power consumption. As flip-flops designed with conventional CMOS logic consume more power than flip-flops designed using transmission gates and pass transistors, and a gated flip-flops will reduce the un-necessary switching of transistors when the input and the output is same. Hence a gated flip-flop using transmission gate and pass transistors are used to reduce the average power consumption. In this paper a gated flip-flop is proposed and its power dissipation Vs input frequency results are compared w.r.t clocked pair-shared flip-flop (CPSFF).Tanner EDA tool is used with 180nm technology. Cadence EDA tool is used to design the lay out

Author - Dinesh Sale, Ashwani Rana

Citation - Dinesh Sale   ,   Ashwani Rana   ,   Dinesh Sale, Ashwani Rana " Conditional Data D Flip-Flop Design Using Pass Transistors For Low Power Application " , International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-2,Issue-8  ( Aug, 2014 )

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