International Journal of Industrial Electronics and Electrical Engineering(IJIEEE).
Paper Title - Design and Implementation of I2C Bus Protocol on FPGA using VERILOG for EEPROM
The I2C or Inter-Integrated Circuit protocol is a serial communication protocol designed by Philip
semiconductors now termed as NXP semiconductors. This paradigm has been proliferating its use in serial communication.
I2C is a bidirectional 2-wire bus designed to enhance hardware efficiency and increase simplicity of the circuit. This
protocol bolsters multiple masters (which is a limitation with SPI communication) and multiple slaves and also allows
communication between faster and slower devices by a serial data bus (SDA) without data loss. The other line is Serial clock
line (SCL) which transfers the data according to a synchronized clock which is a limitation for UART communication. Other
types of communication protocols like USB, RS-422, RS-485, CAN etc. require more pin connections and signals for
communication. The postulates of I2C over UART, SPI, USB and other protocols indicates I2C’s significance in its use as
communication protocol. This paper makes use of Verilog language in designing and Implementing I2C bus on FPGA
(XC3S100E of SPATAN-3E) which acts as master, for interfacing with EEPROM (24C02) which acts as slave. This design
makes use of Xilinx 14.2 version for design and Implementation.
Keywords - Verilog, I2C, SDA, SCL, FPGA, Master, Slave, HDL.
Author - Abhinav Boddupalli
Citation - Abhinav Boddupalli ,
Abhinav Boddupalli " Design and Implementation of I2C Bus Protocol on FPGA using VERILOG for EEPROM " ,
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE) , Volume-5,Issue-12 ( Dec, 2017 )