Paper Title
Design Of Vedic Multiplier For Complex Numbers For Enhanced Computation Using VHDL
Abstract
The main emphasis of this paper is to propose the design of 8 Bit Vedic Multiplier using the techniques of
Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient
system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency
of Urdhva tiryakbhyam – Vedic method for multiplication which strikes a difference in the actual process of multiplication
itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled
to higher bit levels. So the design complexity gets reduced for inputs of larger no of bits and modularity gets increased. The
proposed Vedic multiplier is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language),
synthesized and simulated using EDA (Electronic Design Automation) tool – Xilinx9.1i The main design features of the proposed system are the reconfigurability and flexibility