FPGA Implementation of Non-Blocking Multi-Favour NOC Smart Router using Flexible Crossbar Switch
Network-on-chip (NoC) routers should provide high-speed, cost-effective contention resolution scheme when
multiple packets from different input ports compete for the same output port. The blocking problem in wireless networks
degrades network performance and consequently the performance of the whole system. In the meantime, the main option for
dealing with this problem is the use of non-blocking crossbar networks. The number of pins on a VLSI chip cannot exceed a
few hundred, which restricts the size of the largest crossbar that should be integrated into a single VLSI chip. In this paper,
we contribute to crossbar switch design to propose a non-blocking multi-favour NoC smart (NB-MFS) router. The proposed
flexible crossbar switch can tackle the blocking problem efficiently and eliminates the scalability issue due to the use of
small-size networks as switching elements. The proposed NB-MFS router supports all network topologies sizes within 8×8
and without the necessity to reconfigure the hardware structure. The proposed NB-MFS NoC router is implemented and
synthesized in automotive Spartan6 (XA6SLX9) FPGA device in Xilinx tool. The performance analysis shows that the
proposed NB-MFS router performs very effective than conventional routers in terms of hardware utilization, maximum clock
frequency, and power consumption.
Keywords - Field programmable gate array (FPGA), non-blocking problem, non-blocking smart router, flexible crossbar
switch, non-blocking multi-favour NoC smart (NB-MFS) router.