Design of Multilevel Inverter Using Nested Topologies
This paper involves with design of multilevel inverter using nested multilevel topology based on the technique of
nested arrangement. As compared to the equivalent neutral point clamped inverter (NPC) topology, it has the advantages of
reduced number of diodes and consequently gives higher efficiency. This technique presents an optimized pulse width
modulation strategy that provides synthesizing voltage waveforms with higher quality, and less losses comparison with NPC
topology. The simulation of Nested multilevel topology is to be proven for four, five & six levels and performance is to be
compared in terms of total harmonic distortion (THD). In addition, the PMSM motor is to be fed with this nested multilevel
converter with different output voltage levels and performance comparison is to be accomplished in terms of torque ripples.
The simulation is performed by using MATLAB/Simulink software.
Keywords - DC-AC power converters, multi level inverters, power electronics, pulse width modulation technique,
permanent magnet synchronous motor.