Paper Title
Design of Multi – Master I2cbus Controller

This paper presents design and implementation of Multi – Master Inter – Integrated Circuit (often written as or IIC) Bus Controller. The Multi – Master C Bus Interface is a circuit to perform serial communication based on data format transfer. The arbitration lost detect function makes multi master communication possible. The communication is done on four modes of data transfer depending on the application. The module was designed in Verilog HDL. It is simulated and synthesized using Xilinx Design Suite 13.2 Index Terms- C, Master, Serial data communication, Slave, Xilinx.