Paper Title
Area Efficient High Performance Mac for DSP Applications

In many DSP application multipliers are playing major role. For any embedded based DSP wireless application we propose Vedic method for multiplication of binary numbers which strikes a difference in the actual process of multiplication itself. It enables parallel generation of partial products and eliminates unwanted multiplication steps. The proposed algorithm is modeled using Verilog, a hardware description language. The propagation time of the proposed architecture Vedic multiplier is 3.433ns. Implementation has been done for the ALTERA FPGA device, CYCLONE-III. We can run this core up to several MHz under normal operating conditions and with all the input signals having normal inputs. The results shows that multiplier implemented using Vedic multiplication is efficient in terms of area and speed compared to its implementation using Array and Booth multiplier architectures.