Design of ALU Using Reversible Gates and Vectored Logic
The primary goal of digital modules is to compute the input based on the application. ALU is a key factor of
this computation process. Digital circuits with reversible multiplexer logic gives lesser delay when compared to basic
logic gates. In this research analysis we have implemented a decoder controlled 16 bit ALU, along with vectored
multiplexer selection output. All arithmetic and logic modules are implemented in reversible multiplexer logic by which
delay is reduced along with power consumption. This design analysis is done with VHDL and simulated using ISIM
simulator and implemented using Xilinx ISE project navigator.
Keywords - ALU (arithmetic and Logic Unit), reversible logic, Vectored multiplexer, VHDL.