Implementation of UART With Multiple Input Signature Register For Full Fault Coverage
In communication over the highly secured line the genuineness and the time of occurrence of data is primary
requirement. Design engineers who do not design systems with full testability feature increases the possibility of product
failure and missing market opportunities. This paper mainly focus on the detection of data corruption and delay faults,
incorporated in the data during transmission over the communication link. Thus, for increasing durability and the speed of
fault recognition of datum, it is required to embed the testing property within the universal asynchronous receive/transmit
(UART) chip with less area overhead. BIST is a designing procedure that allows a system to test itself. Designing begins by
implementing the UART module with multiple input signature register (MISR) and a tester using Verilog HDL. The
modules are then, assembled, optimize for minimum hardware requirement, synthesized and tested on Spartan - 3E FPGA
board to verify design.
Keywords— UART, MISR, FPGA, HDL.