Paper Title
Design Of 7-Bit Flash ADC With Fully Differential Architecture

A 7-bit Flash Analog to Digital converter, with fully differential architecture, operating under a clock frequency of 100MHz is implemented in this paper. Architecture is impl-mented for a fully differential swing from -600mV to +600mV with reference voltages ranging from 600mV to 1200mV. The architecture comprises of a resistor ladder of 128 resistors, with the threshold voltages fed into 127 comparators, followed by one hot encoding of the thermometer codes. The output is converted into binary codes by a Binary ROM. Output is verified using an ideal 7-bit Digital to Analog converter. Computation of Signal to Noise ratio and Spurious Free Dynamic Range is done for comparing the performance of the converter. Index Terms- Flash ADC, Kickback Noise, One Hot Encoding, Thermometer coding, Binary ROM