Paper Title
A 16-Bit 2nd Order Incremental Feed-Forward Sigma-Delta Modulator

The paper presents a systematic implementation of 16-bit second order incremental FFSDM designed for DC sensor applications. The non-idealities that affect the performance of the modulator are analyzed in detail. The first stage integrator design with an op-amp gain of 90dB that is robust to the nonidealities is described. The modulator achieves a performance of 97dB SNDR with an OSR of 512 after second order (brick-wall) cascaded-integrator decimation filtering. Keywords—Sigma-Delta Modulator, Switch-Capacitor Integrator, Incremental ADC.