A Novel Approach For Leakage Power Reduction Techniques in CMOS VLSI Circuits
CMOS technology is the key element in the development of VLSI systems because CMOS circuits consume
very little power. Leakage power dissipation has become an overriding concern in nanometer CMOS technologies.
International Technology Roadmap for Semiconductors (IRTS) reports that leakage power dissipation may come to
dominate total power consumption. A comprehensive study and analysis of various leakage power minimization techniques
like Base Case, Forced Stack, Sleep Transistor and Sleepy Stack etc. have been proposed in this paper. In this paper new
methods have been proposed for leakage power reduction in 45 nm technology. The performance parameters of proposed
methods are compared with the previous standard leakage reduction techniques using microwind software and reported in
Index Terms— Leakage power, Sub-threshold leakage power, Sleep transistor, Variable body biasing.