Paper Title
UART IP Core Verification By Using UVM

The objective of this paper is to verify the Universal Asynchronous Receiver/Transmitter (UART) protocol using Universal Verification Methodology (UVM). The UART allows serial communication between two systems running in different operating-frequencies, by converting parallel data into serial form and transmitting serially in frames. The frames are collected in the receiver by receiving bit-by-bit of a frame. Once the frame is collected, it converts the serial data into parallel data. This UART IP core is designed compatible with the industry standard National Semiconductors 16550A device. The key features of this paper are using an 8-bit WISHBONE interface, 16 bit FIFO in UART. RTL logic is written using Verilog HDL. It is verified using UVM test bench methodology. The main aim of this paper is to get 100% functional coverage by doing regression test cases. The UART also generates interrupts, which indicate errors, during transmission of data. The errors may arise due to mismatches in framing of transmitted data, parity-detection, etc. The operation of UART is simulated using Riviera Pro software. The result obtained in this paper is 100% functional coverage. Keywords— UART,UVM,Wishbone interface,FIFO,IP Core.