A Review On FPGA Implementation Of Reconfigurable Digital Fir Filter
This paper presents, the different methods viz. conversion based approaches and memory based methods that
used for efficient implementation of FIR filter. The formulation of distributed arithmetic (DA) is also discussed. The
distributed arithmetic is an efficient technique of FIR filter implementation in terms of area. By using Look Up Table (LUT),
shift registers and scaling accumulator the DA based techniques design. Our ultimate goal is to minimize the parameters
namely, area and power, with the reduction of hardware in terms of multipliers. The literature review of FIR filter by using
DA and other technique is discussed.
Index Terms— Distributed Arithmetic, RAM based LUT; Conversion based approach, FIR Filter, Field Programmable
Gate Array, MAC.