Paper Title
Fast & Error Resilient Processing Unit Of Corner Detection For The Application Of Noise Based Corner Detection Scheme

In present era every multimedia device requires fast and good quality image/video. There is a rapid demand of real time transmission applications so for those applications there is need of some application specific processing unit which should also make justice with battery power consumption. As we know in present stage there are some areas where we need to find the corner points related to Defence, Aeronautics, Traffic. In this type of application there is need of some device which will detect the corner points. In this application there is need of fast processing unit which is not possible by pure accurate unit so for reduction of those issue in this work we will present a novel error resilient algorithm and architecture which will reduce all previous problems. Here we also design our own hardware unit using VLSI technology which is based on powerful HDL “verilog”. Our main motto is to make justice with SPAA(Speed, Power, Area & Accuracy) Metrics. For application analysis we will use Noise based Corner Detection because here we have to verify the quality level of our proposed corner detection. For quality analysis we will use Image quality parameters. In this thesis we are presenting an novel algorithm which is based on fxed point logic. I will compare my proposed algorithm & architecture with previous existing approach. Implementation of proposed algorithm will be done by Matlab and hardware implementation will be done by using of Verilog on Xilinx 14.2 simulator. Verification will be done on Modelsim. Index Terms— SPAA, ERROR, HDL, FAST.