Paper Title
PCB Design Of 2.6 GBPS Scalable Modular Image Compression Board For Earth Observation Missions And FPGA Implementation For Payload Data Pre-Processing

Future sub meter resolution cartographic missions carry advanced high resolution cameras capable of producing resolution of the images as small as 0.25m. The data rates of these satellites are as high as several Gbps. The transmission band width in which the data has to be sent to the ground stations is limited. Hence the data needs to be compressed suitably with a certain lossy compression algorithms which, minimizes the distortions. These satellites need to be designed with modular compression units to cater to high data rate requirements. For higher swath requirements there may be multiple units operating simultaneously stacked up together to handle several Gbps of image data. The board is getting designed is multilayer controlled impedance PCB which houses 2 million gate FPGAs, 16 mega bit memory modules and CCSDS image compression ASIC’s. The data interface with payload electronics is designed with Serializer/Deserializer interface. The functions carried out by this PCB include payload data acquisition, alignment and non-uniformity correction, wavelet based compression and CCSDS space packet formation, aux data formatting, transfer frame generation. This project also includes VHDL coding for the FPGA designs. Index Terms- ASIC, CCSDS, Deser, Cartographics, Scalable, Modular, Payload, BDH System