Simulation Of Nanoscale Fully Depleted EJ- SOI Junctionless MOSFET For High Performance
In this paper we represent the design and simulation study of analog circuit performance parameters for
electrically variable ultrashallow junction silicon on insulator (EJ – SOI) junctionless MOSFET. In this paper properties of
both the EJ and Junctionless MOSFETs are combined to form new device structure. The characteristics are compared with
conventional EJ-SOI MOSFET which is having tri-gate structure with extended source and drain. Here effect of side gate
lengths, side gate voltage, and also the thin film thicknesss is investigated. Here we have shown that by making the device as
junctionless mosfet we will achieve greater control over short channel effects for channel lengths even less than 50nm.
Keywords— Electrically Variable ultra- shallow junction (EJ), Silicon-on-insulator (SOI), Short channel effects (SCEs),
Buried Oxide (BOX), Junctionless Transistor.