<strong>Paper Title</strong><br>
Simulation Of Nanoscale Dual-Material Gate Double-Layer Gate- Stack Bulk Planar Junctionless Transistor<br>
<br>

<strong>Abstract</strong><br>
A simulation study of analog and digital parameters of dual material gate bulk planar junctionless transistor are
discussed. The characteristics are demonstrated and compared with DMG BPJLT and Single Material (conventional) Gate
(SMG) BPJLT. The DMG BPJLT presents superior Subthreshold Swing (SS) and reduces Drain Induced Barrier Lowering
(DIBL) as compared with SMG BPJLT. By adjusting the metal work functions; channel potential and electric field
distribution along the channel can be controlled.
Keywords— Bulk Planer Junctionless Transistor (BPJLT),junctionless transistor (JLT),Short Channel Effects(SCE). Dual
material Date Bulk Planer Junctionless Transistor (DMG-BPJLT), single Material Gate (SMG)