Circuit Design And Implementation Of Hysteresis Controlled Boost Converter
In this paper, we achieved hysteresis controlled boost converter. We used the architecture of the charge pump with
hysteresis comparator for low output ripple to achieve boost convert purpose. The characteristic of hysteresis comparator is
to efficiently decrease output ripple, at the same time limit output ripple about 50 mV to 55 mV. Under circumstances of
output load adjust, will still provide fine transient response performance. The peak efficiency is 81.95 % and the power
consumption is 14.46 mW. We used TSMC 0.18 μm CMOS 1P6M process for HSPICE simulation and finished the work of
tape out service. This design in the post-layout simulation with HSPICE under different variation of environment, the
simulation results show that this circuit is functioning properly. The chip area is 0.723 mm x 0.723 mm.
Keywords- Hysteresis, Voltage Booster, Peak Efficiency, Voltage Converter.