Paper Title
Enhanced Robust Architecture Of Single Bit SRAM Cell Using Drowsy Cache And Super Cutoff CMOS Concept

Now-a-days static random access memory (SRAM) has seen a remarkable and rapid progress in power reduction. Improvement in technology scales down the channel length of MOSFET’s which in turn increases the SRAM stability. SRAM design is crucial since there is strong demand for low speed, low leakage, low power and low noise margin in memory thus it is intentionally built using CMOS circuit design. This paper proposes SRAM cell using Super Cutoff CMOS (SCCMOS) and Drowsy Cache concept which reduces the active and standby mode power consumption by enhancing the data stability and read speed. Proposed SRAM cell consists of transmission gate which enables rail to rail swing, Sleep Stack with Keeper Approach. SRAM cell performance depends upon SNM (signal to noise margin) which is improved with the use of transmission gate. Observation is mainly focused on parameters like Read and Write Delay, Average Power, Leakage Power and PDP (power delay product). Proposed SRAM gives 40-60% reduction in Leakage Power Consumption considering power supply voltage of 1.8V and 10-20% decrease in read and write delay. SRAM Architecture with its peripherals is designed, analyzed and implemented in standard gpdk 180nm technology library using Cadence tool. Index Terms—Drowsy Cache Concept, MTCMOS, SCCMOS, Transmission Gate.