Design Of Fixed-Width Booth Multiplier Using MLCP In Fir Application

Multiplier plays an important role in digital signal processing circuits. It requires considerable power and area. Normally a fixed width multiplier is used to reduce the power and area occupied by the multiplier on a chip. The proposed method consists of designing a fixed width multiplier using booth algorithm. It simplifies structure of multiplier to reduce power and improve performance of the circuit. Fixed width multiplier receives two numbers, each of n bit long and produces an n bit product. The direct truncation of least significant part of the product produces the large error in the resultant product if fixed width output is the requirement. This paper proposes a truncation error reducing logic that is multi-level conditional probability (MLCP) which considerably reduces truncation error. Index Termsâ€” MLCP, booth multiplier, fixed width multiplier, truncation.