Paper Title
FPGA-Based Design of LDPC Code for Error Detection and Correction in Nano Devices

Abstract
The development of Low-Density Parity-Check (LDPC) codes was indeed motivated by the limitations of traditional error correction methods like Hamming codes and Reed-Solomon codes, especially in high-density memory systems and nanometer-scale devices. The LDPC code-based method offers a robust solution for detecting multiple adjacent errors in high-density memory systems. Its efficient resource utilization and high detection capability make it ideal for mitigating radiation-induced errors in modern electronic systems, addressing the limitations of existing methods and supporting the reliability of electronic systems as CMOS technology continues to scale down. In this work, a simplified version of Low-Density Parity-Check (LDPC) codes is designed to detect up to errors making them suitable for next-generation CMOS nano devices. The implementation was carried out using hardware description languages (HDL) and synthesized on a Xilinx Virtex-7 FPGA. FPGA based synthesis results showed that the proposed LDPC code achieved a 57% and 22.14% reduction in area compared to the original method and reduction method respectively. It also maintains the same level of error detection performance and power consumption. This work significantly contributes to the field of error correction in nanometer-scale devices, paving the way for future advancements in semiconductor technology. Future work includes enhancing LDPC codes for stronger error correction in emerging memories like Magnetoresistive Random-Access Memory (MRAM). Keywords - LDPC codes, FPGA, Adjacent Error Correction, Soft Errors, Nanometer Reliability, Min-Sum Algorithm