Paper Title
An Analog Receiver Design and Chip Implementation for Optical Coupling Isolation Applications

Abstract
The paper implements the design of the receiver circuit applied to the optically coupled isolation system. The receiver system architecture is mainly divided into two parts, including an analog low-pass filter used to attenuate the highfrequency quantization noise of the transmission-side delta-sigma modulator. The internal circuit mainly consists of a thirdorder Butterworth low-pass filter, a clock data recovery circuit to generate the filter input clock and data signals. The internal circuits include a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator. Matlab simulation is used to design the transmission-side delta-sigma modulator (SDM) to generate 1-bit digital signals, and the signal-to-noise distortion ratio is 85.74dB as the input signal for the subsequent receiver. The filter circuit architecture adopts a switchedcapacitor filter to achieve higher linearity, realizing the demand for the analog signal ENOB of greater than 12 bits in the receiver. For the clock data recovery circuit, the sampling frequency (20.48 MHz) is the target frequency, and a relatively low-speed Hogge linear phase detector is used for the jittery loop application. The loop filter uses a filter with amplified capacitors for a dual-path charge pump to reduce chip area. The voltage-controlled oscillator uses a five-stage currentsteering inverter to generate delayed and oscillating signals. The circuit adopts TSMC 0.18μm CMOS 1P6M process, with a chip area of approximately 1.0542×0.969695 mm2. The power supply voltage is 1.8V, and the overall circuit power consumption is 6.01 mW. The circuit bandwidth is 40 kHz, oversampling ratio (OSR) is 256, sampling frequency is 20.48 MHz. The signal-to-noise ratio (SNR) is 79.97 dB, total harmonic distortion (THD) is -83.56 dB, signal-to-noise and distortion ratio (SNDR) is 78.4 dB, and effective number of bits (ENOB) is 12.92 bits. Keywords - Delta-Sigma Modulator, Switched-Capacitor Filter, Clock Data Recovery Circuit