Paper Title
Comparison of Different D Flip-Flops Topologies on the Basis of Power Dissipation, Propagation Delay and Variability

This paper investigates the propagation delay and power dissipation of various D flipflopcircuits. UsingCadenceVirtuosovariousdesignedflip-flopsarecomparedintermsoftheirpowerdissipation and propagation delay. The flip-flops are designed with the help of CMOS inverter and CMO Stransmission gates using 45 nm technology. Due to scaling, there has been increase in the variation in the CMOS process and thus to avoid the variation there is as greater need of accurate variation model in developing circuit methods. Consecutively, the delay variability of these circuits has been studied to analyses their responses against PVT (i.e., process, voltage and temperature) variations. This comparison helps the designers in choosing the best design depending on its requirement by reporting the flip-flop design with minimum propagation dela and its variability; and power dissipation. Keywords – Power Dissipation, Propagation Delay, D Flip Flop.