A Reconfigurable VLSI Architecture For Mixed Radix FFT

The squaring unit is an important one for different engineering branches like Digital Signal processing, Image processing and as well as the in the communication also. The low complexity and high speed hardware solution is essential one for now a day’s communication system. The literature survey reports the either any one of the thing is taken into consideration for hardware solution like either low complexity or the high speed only. The proposed one aim is both factors are implemented simultationly using Vedic Mathematics. Direct computation of square of a given binary number consumes same amount of recourses of multiplication. Mathematical multiplication is an essential operation in any DSP calculation. In this paper, we propose an hardware architecture solution for the low complexity and high speed square unit using the Vedic mathematics principles. Keywords- Binary number system, Square unit, Vedic Mathematics, VLSI architecture