Paper Title
An Adaptive Clock Glitch Removal Circuitry for Radiation-Resilient Clock Network in Digital SOC

High-energy environmental radiation particles may affect the operational reliability of a System on Chip (SOC). These particles may cause errors in the combinational logic, sequential logic, and even in the clock network. In the latter, they appear as clock glitches that propagate, and eventually, incorrectly latch all the sequential circuits, such as flip-flops and latches attached to the clock node concerned. The impact on chip functionality is usually fatal. In this work, we propose a low-cost adaptive clock glitch removal circuitry for radiation-resilient clock networks. The proposed technique can be adjusted based on the actual clock glitch profile, to ensure that the error in the clock network is removed, while the impact on the clock signal itself is minimized. It is fully synthesizable, and can thus be incorporated in a conventional digital flow. Index Terms - Radiation-Resilient, Clock Network, SEU.