Paper Title
Memory Validation using Fast Symmetric Binary Counters

The memory errors are becoming more and more common because of the vast size of SRAM cache and DRAM memory. This is becoming the major issue for the system developers and the end users. Huge methods are prevailed for detecting and extenuating the memory corruption occurrence like: error detection, error correction, cache scrubbing and array interleaving. The counter circuits increment the address location of the memory bits linearly with time so that each bit is checked for the fault. In order to check through the memory bits and perform the analysis, aid of fast counter circuits is necessary to increase the speed of operation. Use of fast symmetric binary counters increases the overall speed of the process thus producing better results in high end devices. This paper demonstrates the performance of fast symmetric binary counters in memory circuits. The results show that the proposed counters have low latency when compares to the existing circuits. Keywords - SRAM, DRAM, Cache, Fast Symmetric Binary Counters.