Paper Title
Efficient Implementation And Performance Analysis Of Pipelined Architecture For Radix-4 CORDIC With Redundant Arithmetic

Many Digital signal processing (DSP) applications are based on real time constraints. On account of this, conventional processors are not suitable for modern day DSP systems. Thus leading major issues pertaining to latency and throughput .In order to overcome issues and there by improvising in terms of performance, CORDIC is one such hardware efficient algorithm and its current trend of hardware intensive signal processing. In this Paper, the unfolded Radix-2 parallel CORDIC architecture algorithm and to enhance the performance, a pipelined architecture of radix-4 CORDIC rotator with redundant arithmetic is implemented.. The proposed CORDIC architectures are analyzed using MATLAB (version 73. R2011b) tool and are designed using Verilog programming in Xilinx 14.2 FPGA platform. Simulated on ISim simulator and its results are analyzed, verified and compared with MATLAB results. The proposed architecture operates at 154.655MHz where as folded parallel CORDIC architecture operates at 26.36MHz